The Gate Driver on Array, GOA circuit is a circuit for realizing progressive scanning of a display panel. Currently, the driving circuits commonly used in the display panel include a CMOS type GOA circuit and an NMOS type GOA circuit. The CMOS type GOA circuit includes N-channel thin film transistor, NTFT devices and P-channel thin film transistor, PTFT devices; and NMOS-type GOA circuits include only NTFT devices. The GOA control signal line in the NMOS display panel is directly accessed to a first level GOA unit through a WOA trace, and the GOA control signal line needs to go through a large Resistance-Capacitance Circuits, RC circuit, also known as RC filter or RC network and then accessed to a last level GOA unit. In this case, due to the large RC circuit going through, the control signal on the GOA control signal line will be delayed, especially for AC signals such as CK signal (clock signal), so the control signal accessed to the last level GOA unit has a certain degree of delay than accessed to the first level GOA unit, including CK signal, GAS signal (global control signal) and so on. In addition, as shown in FIG. 1, the GOA unit in the conventional NMOS type GOA circuit is shown in FIG. 1, by controlling a potential of Q-point to turn on a thin film transistor NT1, therefore to output a Gate signal (gate control signal) by CK signal, that is, the waveform outputted by the Gate is the CK signal, due to the signal delay mentioned above, delay conditions of the output waveform of the first level GOA unit and the last level GOA unit connected to the first level GOA unit at the same side are inconsistent, that is, the delay degree of the output signal of the first level GOA unit is less, and the delay degree of the output signal of the last level GOA unit is more. As shown in FIG. 2, CK_1 is the waveform of clock signal accessed to the first level GOA unit, and CK_3 is the waveform of clock signal accessed to the next level GOA unit cascaded with the first level GOA unit. It can be seen that the delay is occurred to the clock signal between two GOA units in adjacent cascades; Gate_1 is the waveform of the gate control signal outputted by the first level GOA unit, Gate_M−1 is the waveform of the gate control signal outputted by the last level GOA unit connected to the first level GOA unit, it can be seen that the delay is occurred to the gate control signal outputted by the last level GOA unit.
The occurrence of the condition can cause inconsistencies in the feedthrough voltage across the upper and lower regions of the NMOS display panel, which is the display panel that contains the NMOS-type GOA circuit. As shown in FIG. 3, ΔVa is the feedthrough voltage of the lower region (that is, the region corresponding to the first GOA unit) of an active area AA (the effective display area) of the display panel, ΔVb is the feedthrough voltage of the upper region (that is, the region corresponding to the last level GOA unit connected to the first level GOA unit) of the active area AA of the display panel, it can be seen from FIG. 3, the feedthrough voltages of the upper and lower terminals of the active area AA is significantly inconsistent. The feedthrough voltages of the upper and lower regions of the NMOS display panel are inconsistent to eventually lead to poor flicker uniformity of the upper and lower regions of the NMOS display panel.